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USB 2.0 High-Speed/UART Dual SP3T (Dual 3 to 1 Multiplexer)
ISL54216
The Intersil ISL54216 is a single supply dual SP3T analog switch that operates from a single supply in the range of 2.7V to 4.6V. It was designed to multiplex between three different differential data sources, allowing the multiplexing of USB 2.0 high speed and/or UART data signals through a common headphone connector in Personal Media Players and other portable battery powered devices. The switch channels have very low ON capacitance and high bandwidth to pass USB high speed signals (480Mbps) with minimal edge and phase distortion and can swing rail-to-rail to pass UART and full-speed USB signals. The ISL54216 is available in a tiny 12 Ld 2.2mmx1.4mm ultra-thin QFN and 12 Ld 3mmx3mm TQFN packages. It operates over a temperature range of -40C to +85C.
ISL54216
Features
* High Speed (480Mbps) and Full Speed (12Mbps) Signaling Capability per USB 2.0 on All Ports * UART Capability on All Ports * COM Pins Allow Negative Swings to -2V * Compatible with Wired-OR Connected GND Referenced Audio Sources * All Switches Open Mode * Power OFF Protection * COM Pins Overvoltage Tolerant to 5.5V * Low ON Capacitance @ 240MHz . . . . . . . . . . . . 4pF * -3dB Frequency . . . . . . . . . . . . . . . . . . . . 800MHz * Single Supply Operation (VDD) . . . . . . . 2.7V to 4.6V * Available 12 Ld TQFN and 12 Ld TQFN Packages * Compliant with USB 2.0 Short Circuit Requirements Without Additional External Components * Pb-Free (RoHS Compliant)
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Applications*(see page 15)
* MP3 and Other Personal Media Players * Cellular/Mobile Phone * Readers
Application Block Diagram
3.3V CONTROLLER VDD ISL54216 LOGIC CONTROL 4M
3DUSB TRANSCEIVER 3D+
C0 C1 VBUS
USB/DATA JACK
2DUSB TRANSCEIVER 2D+
COM -
COM + 1DUART 1D+ GND
September 27, 2010 FN7701.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54216
Pin Configuration
12 LD 2.2x1.4 TQFN TOP VIEW
3D12 VDD 11 C0 10 PD 3D+ 1 LOGIC CONTROL 9 C1 LOGIC CONTROL 4M 2D2 8 COM 2D2 8 COM -
12 LD 3x3 TQFN TOP VIEW
3D12 VDD 11 C0 10
4M 9 C1
3D+
1
2D+
3 4M
7 4M
COM +
2D+
3
7
COM +
4 1D-
5 1D+
6 GND
4 1D-
5 1D+
6 GND
NOTE: 1. ISL54216 Switches Shown for C1 = Logic "1" and C0 = Logic "0".
Pin Descriptions
TQFN TQFN NAME 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 PD 3D+ 2D2D+ 1D1D+ GND FUNCTION USB3 Differential Input USB2 Differential Input USB2 Differential Input USB1 Differential Input USB1 Differential Input Ground Connection
Truth Table
C1 0 0 1 1 C0 0 1 0 1 MODE Wired-OR Audio USB/UART #1 USB/UART #2 USB/UART #3 COMMENTS All switches open 1D- and 1D+ ON 2D- and 2D+ ON 3D- and 3D+ ON
C0, C1: Logic "0" when 0.5V or float, Logic "1" when 1.4V with VDD in range of 2.7V to 3.6V.
COM+ Data Common Pin COMC1 C0 VDD 3DPD Data Common Pin Digital Control Input Digital Control Input Power Supply USB3 Differential Input Thermal Pad. Tie to Ground or Float
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Ordering Information
PART NUMBER ISL54216IRUZ-T (Notes 2, 3) ISL54216IRTZ (Note 4) ISL54216IRTZ-T (Note 2, 4) ISL54216EVAL1Z NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54216. For more information on MSL please see techbrief TB363. PART MARKING GY 4216 4216 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 12 Ld 2.2mmx1.4mm TQFN (Tape and Reel) 12 Ld 3mmx3mm TQFN 12 Ld 3mmx3mm TQFN (Tape and Reel) PKG. DWG. # L12.2.2x1.4A L12.3x3A L12.3x3A
Evaluation Board
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ISL54216
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V Input Voltages 1D+, 1D-, 2D+, 2D-, 3D+, 3D- . . . . . . . . . . . .-2V to 5.5V C0, C1 (Note 6) . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V Output Voltages COM-, COM+ . . . . . . . . . . . . . . . . . . . . . . . . .-2V to 5.5V Continuous Current (1D-, 1D+, 2D-, 2D+, 3D-, 3D+) . . 40mA Peak Current (1D-, 1D+, 2D-, 2D+, 3D-, 3D+) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . 100mA ESD Rating: Human Body Model (Tested per JESD22-A114F) . . . . >5kV Machine Model (Tested per JESD22-A115B). . . . . . . >400V Charged Device Model (Tested per JESD22-C110D) . . >2kV Latch-up (Tested per JESD-78B; Class 2, Level A) . . . at +85C
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 12 Ld TQFN Package (Notes 7, 10) 155 90 12 Ld TQFN Package (Notes 8, 9) . 58 1.0 Maximum Junction Temperature (Plastic Package) . . +150C Maximum Storage Temperature Range . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage Range . . . . . . . . . . . . . . . . . . . 2.7V to 4.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 6. Signals on C1 and C0 exceeding GND by specified amount are clamped. Limit current to maximum current ratings. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 9. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 10. For JC, the "case temp" location is taken at the package top center.
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VC0H, VC1H = 1.4V,
VC0L, VC1L= 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40C to +85C. MAX MIN (Notes TEMP (Notes (C) 12, 13) TYP 12, 13) UNITS Full 25 Full 25 Full 25 Full +25 Full 25 Full 25 Full 25 25 25 25 -1 -15 -20 -20 -25 6 0.07 0.32 9.5 125 125 30 75 VDD 8 10 0.5 0.55 0.8 1.2 15 20 15 20 20 25 V nA nA nA nA ns ns ns ps
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
TEST CONDITIONS VDD = 2.7V to 4.6V VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = 0V to 400mV (see Figure 3, Note 15)
rON Matching Between Channels, VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = Voltage at rON max rON, (Notes 15, 16) rON Flatness, RFLAT(ON) ON-Resistance, rON OFF Leakage Current, IXD+(OFF) or IXD-(OFF), ICOMX(OFF) VDD = 2.7V, ICOMx = 17mA, VD+ or VD- = 0V to 400mV, (Notes 14, 15) VDD = 3.3V, ICOMx = 17mA, VD+ or VD- = 3.3V (See Figure 3, Note 15) VDD = 4.6V, All OFF Mode (C0 = 0.5V, C1 = 0.5V), VCOM- or VCOM+ = 0.3V, 3.3V, VXD+ or VXD- = 3.3V, 0.3V
ON Leakage Current, IXD+(ON) or VDD = 4.6V, VXD+ or VXD- = 0.3V, 3.3V, VCOM- or IXD-(ON), ICOMX(ON) VCOM+ = 0.3V, 3.3V DPDT DYNAMIC CHARACTERISTICS All OFF to ON or ON to All OFF Address Transition Time, tTRANS Data Channel to Data Channel Address Transition Time, tTRANS Skew, (tSKEWOUT - tSKEWIN) VDD = 2.7V, RL = 50, CL = 10pF, (see Figure 1) VDD = 2.7V, RL = 50, CL = 10pF, (see Figure 1)
Break-Before-Make Time Delay, tD VDD = 3.6V, RL = 50, CL = 10pF, (see Figure 2) VDD = 3.0V, RL = 45, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 6)
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Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VC0H, VC1H = 1.4V,
VC0L, VC1L= 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) MAX MIN (Notes TEMP (Notes (C) 12, 13) TYP 12, 13) UNITS 25 25 25 25 25 25 25 25 210 250 -36 -32 800 3 6 4 ps ps dB dB MHz pF pF pF
PARAMETER Total Jitter, tJ Rise/Fall Degradation (Propagation Delay), tPD Crosstalk OFF-Isolation -3dB Bandwidth OFF Capacitance, CXD+OFF, CXD-OFF
TEST CONDITIONS VDD =3.0V, RL = 50, CL = 10pF, tR = tF = 500ps at 480Mbps VDD = 3.0V, RL = 45, CL = 10pF, (see Figure 6) VDD = 3.0V, RL = 50, f = 240MHz VDD = 3.0V, RL = 50, f = 240MHz Signal = 0dBm, 0.2VDC offset, RL = 50, CL = 5pF f = 1MHz, VDD = 3.0V (see Figure 4)
COM ON Capacitance, CCOM-(ON), f = 1MHz, VDD = 3.0V (see Figure 4) CCOM+(ON) COM ON Capacitance, CCOM-(ON), f = 240MHz, VDD = 3.0V CCOM+(ON) POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD (ALL OFF Mode) Positive Supply Current, IDD (USB1 Mode) Positive Supply Current, IDD (USB2 Mode) Positive Supply Current, IDD (USB3 Mode) VDD = 3.6V, C1 = GND, C0 = GND VDD = 3.6V, C1 = GND, C0 = VDD VDD = 3.6V, C1 = VDD, C0 = GND VDD = 3.6V, C0 = C1 = VDD
Full 25 Full 25 Full 25 Full 25 Full 25 25 25
2.7 6.5 6.5 6.5 6.5 11 5
4.6 8 15 8 15 8 15 8 15 1 -
V A A A A A A A A A A A
Power OFF COMx Current, ICOMx VDD = 0V, C0 = C1 = Float, COMx = 5.25V Power OFF Logic Current, IC0, IC1 VDD = 0V, C0 = C1 = 5.25V Power OFF D+/D- Current, IXD+, VDD = 0V, C0 = C1 = Float, XD- = XD+ = 5.25V IXDDIGITAL INPUT CHARACTERISTICS C0, C1 Voltage Low, VC0L, VC1L C0, C1 Input Current, IC0L, IC1L C0, C1 Pull-Down Resistor, RCx NOTES: 11. Vlogic = Input voltage to perform proper function. VDD = 2.7V to 3.6V VDD = 3.6V, C0 = C1 = 0V or Float VDD = 3.6V, C0 = C1 = 3.6V, Measure current into C0 or C1 pin and calculate resistance value.
Full Full Full Full Full
1.4 -50 -2 -
6.2 1.6 4
0.5 5.25 50 2 -
V V nA A M
C0, C1 Voltage High, VC0H, VC1H VDD = 2.7V to 3.6V C0, C1 Input Current, IC0H, IC1H VDD = 3.6V, C0 = C1 = 3.6V
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 15. Limits established by characterization and are not production tested. 16. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between 1D+ and 1D- or between 2D+ and 2D- or between 3D+ and 3D-.
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Test Circuits and Waveforms
VC0,C1 LOGIC INPUT VC0,C1 50% tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT tr < 20ns tf < 20ns VINPUT SWITCH INPUT C0, C1 GND RL 50 CL 10pF COMx VDD C
VOUT
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (INPUT) R + r L ON FIGURE 1B. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1A. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
VDD
C
3D- OR 3D+ LOGIC INPUT VC0 VC1 VOUT 0V VINPUT 2D- OR 2D+ 1D- OR 1D+ C0, C1 SWITCH OUTPUT 90% tD LOGIC INPUT GND COMx RL 50 VOUT CL 10pF
Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD C VDD C
rON = V1/17mA xD- OR xD+ VD- OR VD+ C0 V1 17mA COMx GND C1 0V VDD IMPEDANCE ANALYZER COMx
CTRL xD- OR xD+
VCx VCxL OR VCxH GND
Repeat test for all switches. FIGURE 3. rON TEST CIRCUIT
Repeat test for all switches.
FIGURE 4. CAPACITANCE TEST CIRCUIT
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Test Circuits and Waveforms (Continued)
VDD C
CTRL SIGNAL GENERATOR xDCOMx 50
VCx 0V OR FLOAT
ANALYZER 50
COMx GND
xD+
N.C.
FIGURE 5. CROSSTALK TEST CIRCUIT
VDD tri 90% DIN+ DIN10% 50% tskew_i 90% 50% 10% tfi tro 90% OUT+ OUT10% 50% tskew_o 90% tf0 50% 10% GND DINDIN+ 143 15.8 143 COM0V VDD 15.8 C0 C1 COM+ VDD
C
D+ CL DCL
OUT+ 45 OUT45
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 6A. MEASUREMENT POINTS FIGURE 6. SKEW TEST
FIGURE 6B. TEST CIRCUIT
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Application Block Diagrams
3.3V 100 VDD 3DUSB TRANSCEIVER 3D+ LOGIC CONTROL 4M C0 C1 VBUS USB/DATA JACK HEAD PHONE JACK
FN7701.0 September 27, 2010
CONTROLLER
USB TRANSCEIVER
2D2D+
COM -
COM + 1DUART 1D+ GND ISL54216
AUDIO CODEC
ISL54406
Detailed Description
The ISL54216 device consists of dual SP3T (single pole/triple throw) analog switches. It operates from a single DC power supply in the range of 2.7V to 4.6V. It was designed to function as differential 3 to 1 multiplexer to select between three different differential data signals. Its offered in tiny TQFN and TQFN packages for use in MP3 players, PDAs, cellphones, and other personal media players. A device consists of six 6 data switches. They were designed to pass high-speed USB differential data signals with minimal edge and phase distortion. They can swing rail-to-rail to pass UART and full-speed USB signals. The COM pins can accept signals that swing below ground by as much as -2V. This allows an audio source to be wired-or connected at the COM pins. The ISL54216 was specifically designed for MP3 players, personal media players and cellphone applications that need to combine three differential data channels into a single shared connector, thereby saving space and component cost. This functionality is shown in the Typical Application Block Diagram. A detailed description of the switches is provided in the following sections.
See Figures 11 and 12 for high-speed Eye Pattern taken with switch in the signal path. These switches can also swing rail-to-rail and pass USB full-speed (12Mbps) and UART signals with minimal distortion. See Figure 13 for USB full-speed Eye Pattern taken with switch in the signal path. The maximum normal operating signal range for the USB switches is from -1V to VDD. The signal voltage at D- and D+ should not be allow to exceed the VDD voltage rail or go below ground by more than -1V for normal operation.
Fault Protection and Power-Off Protection
However, in the event that the USB 5.25V VBUS voltage were shorted to one or both of the COM pins, the ISL54216 has fault protection circuitry to prevent damage to the ISL54216 part. The fault circuitry allows the signal pins (COM-, COM+, 1D-, 1D+, 2D-, 2D+, 3D-, 3D+) to be driven up to 5.25V while the VDD supply voltage is in the range of 0V to 4.6V. This fault condition causes no stress to the IC. In addition when VDD is at 0V (ground) all switches are OFF and the fault voltage is isolated from the other side of the switch (Power-Off Protection). When VDD is in the range of 2.7V to 4.6V, the fault voltage will pass through to the output of an active switch channel. Note: During the fault condition normal operation is not guaranteed until the fault condition is removed.
Data Switches
The six data switches (1D+, 1D-, 2D+, 2D-, 3D+, 3D-) are 6 bidirectional switches that were specifically designed to pass high-speed USB differential data signals in the range of 0V to 400mV. The switches have low capacitance and high bandwidth to pass USB high-speed signals (480Mbps) with minimum edge and phase distortion to meet USB 2.0 signal quality specifications. 8
ISL54216 Operation
The discussion that follows will discuss using the ISL54216 in the "Application Block Diagrams" on page 8.
ISL54216
POWER The power supply connected at VDD (pin 11) provides power to the ISL54216 part. Its voltage should be kept in the range of 2.7V to 4.6V. In a typical application, VDD will be in the range of 2.7V to 4.3V and will be connected to the battery or LDO of the MP3 player or cellphone. A 0.01F or 0.1F decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. LOGIC CONTROL The state of the ISL54216 device is determined by the voltage at the C1 pin (pin 9) and the C0 pin (pin 10). Refer to the "Truth Table" on page 2. The C1 pin and C0 pin are internally pulled low through 4M resistors to ground and can be tri-stated or left floating. The C1 pin and C0 pin can be driven with a voltage that is higher than the VDD supply voltage. They can be driven up to 5.25V with the VDD supply in the range of 2.7V to 4.6V. Driving the logic higher than the supply rail will cause the logic current to increase. With VDD = 2.7V and VLOGIC = 5.25V, ILOGIC current is approximately 5.5A. Logic Control Voltage Levels With VDD in the range of 2.7V to 3.6V the logic levels are: C1, C0 = Logic "0" (Low) when 0.5V or Floating. C1, C0 = Logic "1" (High) when 1.4V. ALL SWITCHES OFF Mode If the C1 pin = Logic "0" and C0 pin = Logic "0" the part will be in the ALL SWITCHES OFF mode. In this mode, the 3D- and 3D+ data switches, the 2D- and 2D+ data switches, and the 1D- and 1D+ data switches will be OFF (high impedance). The COM pins can accommodate signals that swing below ground by as much as -2V. This allows an audio CODEC to be connected to the COM pins when the device is in the all off state. USB/UART1 Mode If the C1 pin = Logic "0" and C0 pin = Logic "1" the part will go into USB/UART1 mode. The 1D- and 1D+ switches are ON and the 2D- and 2D+ switches and 3D- and 3D+ will be OFF (high impedance). USB2 Mode If the C1 = Logic "1" and C0 pin = Logic "0" the part will be in the USB/UART2 mode. The 2D- and 2D+ switches will be ON and the 1D- and 1D+ switches and the 3Dand 3D+ will be OFF (high impedance). USB3 Mode If the C1 pin = Logic "1" and C0 pin = Logic "1" the part will be in the USB/UART3 mode. The 3D- and 3D+ switches are ON, and the 1D- and 1D+ switches and 2Dand 2D+ switches will be OFF (high impedance).
Typical Performance Curves
6.7 6.6 6.5 6.4 rON () 6.3 6.2 6.1 6.0 5.9 5.8 0 0.05 0.10 VDD = 4.6V VDD = 3.3V VDD = 3.6V VDD = 3.0V ICOM = 40mA VDD = 2.7V
TA = +25C, Unless Otherwise Specified.
9 VDD = 2.7V ICOM = 40mA
+85C
8
7 rON ()
+25C
6 -40C 5
VDD = 4.0V
4
0.15 0.20 0.25 VCOM (V)
0.30
0.35
0.40
3 0
0.05
0.10
0.15 0.20 0.25 VCOM (V)
0.30
0.35
0.40
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
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Typical Performance Curves
9 8 7 rON () 6 5 4 3 -40C VDD = 3.3V ICOM = 40mA +85C
TA = +25C, Unless Otherwise Specified. (Continued)
16 14 12 rON () VDD = 3.3V ICOM = 40mA
+25C
10 8 6 4 2
+85C
+25C
-40C
0
0.05
0.10
0.15 0.20 0.25 VCOM (V)
0.30
0.35
0.40
0
0.5
1.0
1.5 2.0 VCOM (V)
2.5
3.0 3.3
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE vs TEMPERATURE
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Typical Performance Curves
TA = +25C, Unless Otherwise Specified. (Continued)
VDD = 2.7V USB NEAR END MASK
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 11. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
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Typical Performance Curves
TA = +25C, Unless Otherwise Specified. (Continued)
VDD = 2.7V USB FAR END MASK
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 12. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
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Typical Performance Curves
TA = +25C, Unless Otherwise Specified. (Continued)
VDD = 2.7V
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 13. EYE PATTERN: 12Mbps USB SIGNAL WITH USB SWITCHES IN THE SIGNAL PATH
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Typical Performance Curves
-20 RL = 50 VIN = 0.2VP-P to 2VP-P
TA = +25C, Unless Otherwise Specified. (Continued)
1 0 -1 NORMALIZED GAIN (dB) -2 -3 -4
-40 NORMALIZED GAIN (dB)
-60
-80
-100
-120
RL = 50 VIN = 0dBm, 0.86VDC BIAS
-140 0.001
0.01
0.1
1M
10M
100M 500M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 14. OFF-ISOLATION USB SWITCHES
FIGURE 15. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE AND TQFN THERMAL PAD POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 837 PROCESS: Submicron CMOS
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Revision History
DATE 9/27/10 REVISION FN7701.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL54216 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN7701.0 September 27, 2010
ISL54216
Package Outline Drawing
L12.3x3A
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 0, 09/07
3.00 A B 6 PIN 1 INDEX AREA 9 4X 1.45 3.00 1 10 0.5 BSC 6 PIN #1 INDEX AREA
12
7 3 0.10 M C A B (4X) 0.15 6 12X 0 . 4 0 . 1 4 4 0.25 +0.05 / -0.07
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X" 0.10 C BASE PLANE 1.45 ) SEATING PLANE 0.08 C
0 . 75 ( 2 . 8 TYP )
C
SIDE VIEW
(
0.6 C 0 . 2 REF 5
0 . 50 0 . 25
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
16
FN7701.0 September 27, 2010
ISL54216 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D 6 INDEX AREA 2X 2X 0.10C 1 0.10C 2 A
L12.2.2x1.4A
B
12 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A3 b D 0.15 2.15 1.35 MIN 0.45 NOMINAL 0.50 0.127 REF 0.20 2.20 1.40 0.40 BSC 0.20 0.35 0.40 12 3 3 0 12 0.45 0.25 2.25 1.45 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 0 12/06
N
E
TOP VIEW
0.10C C
E e k
A 0.05C
A1
L N Nd
SIDE VIEW
LEADS COPLANARITY
Ne NOTES:
(DATUM A) PIN #1 ID 12 e (DATUM B) NX b Nd 3 5 0.10 M A B C 0.05 M C NX L
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
L 1.50
Ne
BOTTOM VIEW
C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1)
2.30
1 2 3 0.40 0.45 (12x) 0.25 (12x) 0.40
TYPICAL RECOMMENDED LAND PATTERN
10
17
FN7701.0 September 27, 2010

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